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Freescale Semiconductor Data Sheet: Technical Data
Document Number: MCF5329DS Rev. 4, 04/2008
MCF5329
MAPBGA-256 17mm x 17mm MAPBGA-196 15mm x 15mm
MCF532x ColdFire(R) Microprocessor Data Sheet
Features * Version 3 ColdFire variable-length RISC processor core * System debug support * JTAG support for system level board testing * On-chip memories - 16-Kbyte unified write-back cache - 32-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters (e.g., DMA, FEC, LCD controller, and USB host and OTG) * Power management * Liquid Crystal Display Controller (LCDC) * Embedded Voice-over-IP (VoIP) system solution * SDR/DDR SDRAM Controller * Universal Serial Bus (USB) Host Controller * Universal Serial Bus (USB) On-the-Go (OTG) controller * Synchronous Serial Interface (SSI) * Fast Ethernet Controller (FEC) * Cryptography Hardware Accelerators * FlexCAN Module * Three Universal Asynchronous Receiver Transmitters (UARTs) * I2C Module * Queued Serial Peripheral Interface (QSPI) * Pulse Width Modulation (PWM) module * Real Time Clock * Four 32-bit DMA Timers * Software Watchdog Timer * Four Periodic Interrupt Timers (PITs) * Phase Locked Loop (PLL) * Interrupt Controllers (x2) * DMA Controller * FlexBus (External Interface) * Chip Configuration Module (CCM) * Reset Controller * General Purpose I/O interface
(c) Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1 2 3 MCF532x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . .3 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .5 3.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.3 Supply Voltage Sequencing and Separation Cautions . .5 3.3.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .5 3.3.2 Power Down Sequence . . . . . . . . . . . . . . . . . . . .6 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .6 4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4.2 Pinout--256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .14 4.3 Pinout--196 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .15 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .17 5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .18 5.5 Oscillator and PLL Electrical Characteristics . . . . . . . .19 5.6 External Interface Timing Characteristics . . . . . . . . . . .20 5.6.1 FlexBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.7 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.7.1 SDR SDRAM AC Timing Characteristics. . . . . .23 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.7.2 DDR SDRAM AC Timing Characteristics . . . . . General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . Reset and Configuration Override Timing . . . . . . . . . . LCD Controller Timing Specifications . . . . . . . . . . . . . USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ULPI Timing Specification . . . . . . . . . . . . . . . . . . . . . . SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . I2C Input/Output Timing Specifications . . . . . . . . . . . . Fast Ethernet AC Timing Specifications . . . . . . . . . . . 5.15.1 MII Receive Signal Timing . . . . . . . . . . . . . . . . 5.15.2 MII Transmit Signal Timing . . . . . . . . . . . . . . . . 5.15.3 MII Async Inputs Signal Timing . . . . . . . . . . . . 5.15.4 MII Serial Management Channel Timing . . . . . 5.16 32-Bit Timer Module Timing Specifications . . . . . . . . . 5.17 QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . 5.18 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 5.19 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Package Dimensions--256 MAPBGA . . . . . . . . . . . . . 7.2 Package Dimensions--196 MAPBGA . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 28 29 30 33 33 33 35 37 37 37 38 38 39 39 40 42 42 46 46 47 48
4
5
6 7
8
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 2 Freescale Semiconductor
MCF532x Family Comparison
USB OTG
(To/From SRAM backdoor)
FlexBus Chip Selects External Interface USB OTG USB Host LCDC SDRAMC QSPI I 2C UART SDRAMC PADI -- Pin Muxing PWM DMA Timer FEC CANRX CANTX SSI DREQn DACKn D[31:0] A[23:0] R/W CS[5:0] TA TS BE/BWE[3:0] JTAG TAP
USB Host (To/From PADI)
M5 M4
M6 XBS
S4
S1
SDRAMC
LCDC M2 M1 S7 M0 S6 Cryptography Modules RNGA INTC0
(To/From PADI) FEC
SKHA MDHA
INTC1
DMA Timers (To/From PADI) DMA
FlexCAN
I2C
QSPI
UARTs
DIV ULPI Interface XCVR XCVR
EMAC BDM TRST TCLK TMS TDI TDO JTAG_EN
V3 ColdFire CPU
PORTS SDRAMC SSI LCDC RTC EXTAL32K XTAL32K 16 KByte Cache (1024x32)x4
(To/From PADI)
USB OTG USB Host PWMs, EPORT, Watchdog, PITs
RESET RCON RSTOUT
Reset PLL CLKOUT
32 KByte SRAM (4096x32)x2
EXTAL
XTAL
(To/From XBS backdoor)
Figure 1. MCF5329 Block Diagram
1
MCF532x Family Comparison
Table 1. MCF532x Family Configurations
Module ColdFire Version 3 Core with EMAC (Enhanced Multiply-Accumulate Unit) Core (System) Clock Peripheral and External Bus Clock (Core clock / 3) Performance (Dhrystone/2.1 MIPS) Unified Cache Static RAM (SRAM) MCF5327 * MCF5328 * MCF53281 * MCF5329 *
The following table compares the various device derivatives available within the MCF532x family.
up to 240 MHz up to 80 MHz up to 211 16 Kbytes 32 Kbytes
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 3
Ordering Information
Table 1. MCF532x Family Configurations (continued)
Module LCD Controller SDR/DDR SDRAM Controller USB 2.0 Host USB 2.0 On-the-Go UTMI+ Low Pin Interface (ULPI) Synchronous Serial Interface (SSI) Fast Ethernet Controller (FEC) Cryptography Hardware Accelerators Embedded Voice-over-IP System Solution FlexCAN 2.0B communication module UARTs I2C QSPI PWM Module Real Time Clock 32-bit DMA Timers Watchdog Timer (WDT) Periodic Interrupt Timers (PIT) Edge Port Module (EPORT) Interrupt Controllers (INTC) 16-channel Direct Memory Access (DMA) FlexBus External Interface General Purpose I/O Module (GPIO) JTAG - IEEE(R) 1149.1 Test Access Port Package MCF5327 * * * * -- * -- -- -- -- 3 * * * * 4 * 4 * 2 * * * * 196 MAPBGA MCF5328 * * * * * * * -- -- -- 3 * * * * 4 * 4 * 2 * * * * 256 MAPBGA MCF53281 * * * * * * * -- * * 3 * * * * 4 * 4 * 2 * * * * 256 MAPBGA MCF5329 * * * * * * * * -- * 3 * * * * 4 * 4 * 2 * * * * 256 MAPBGA
2
Ordering Information
Table 2. Orderable Part Numbers
Freescale Part Number MCF5327CVM240 MCF5328CVM240 MCF53281CVM240 MCF5329CVM240 Description MCF5327 RISC Microprocessor MCF5328 RISC Microprocessor MCF53281 RISC Microprocessor MCF5329 RISC Microprocessor Package 196 MAPBGA 256 MAPBGA 256 MAPBGA 256 MAPBGA Speed 240 MHz 240 MHz 240 MHz 240 MHz Temperature -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 4 Freescale Semiconductor
Hardware Design Considerations
3
3.1
Hardware Design Considerations
PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in Figure 2 should be connected between the board VDD and the PLLVDD pins. The resistor and capacitors should be placed as close to the dedicated PLLVDD pin as possible.
10 Board IVDD 10 F 0.1 F PLL VDD Pin
GND
Figure 2. System PLL VDD Power Filter
3.2
USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 3 should be connected between the board EVDD or IVDD and each of the USBVDD pins. The resistor and capacitors should be placed as close to the dedicated USBVDD pin as possible.
0 Board EVDD 10 F 0.1 F USB VDD Pin
GND
Figure 3. USB VDD Power Filter
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel with those shown.
3.3
Supply Voltage Sequencing and Separation Cautions
The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. SDVDD (2.5V or 3.3V) and EVDD are specified relative to IVDD.
3.3.1
Power Up Sequence
If EVDD/SDVDD are powered up with IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD must powered up. IVDD should not lead the EVDD, SDVDD, or PLLVDD by more than 0.4 V during power ramp-up or there is
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 5
Pin Assignments and Reset States
high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 500 us to avoid turning on the internal ESD protection clamp diodes.
3.3.2
Power Down Sequence
If IVDD/PLLVDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state. There is no limit on how long after IVDD and PLLVDD power down before EVDD or SDVDD must power down. IVDD should not lag EVDD, SDVDD, or PLLVDD going low by more than 0.4 V during power down or there is undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: 1. 2. Drop IVDD/PLLVDD to 0 V. Drop EVDD/SDVDD supplies.
4
4.1
Pin Assignments and Reset States
Signal Multiplexing
The following table lists all the MCF532x pins grouped by function. The Dir column is the direction for the primary function of the pin only. Refer to Section 7, "Package Information," for package diagrams. For a more detailed discussion of the MCF532x signals, consult the MCF5329 Reference Manual (MCF5329RM).
NOTE
In this table and throughout this document, a single signal within a group is designated without square brackets (i.e., A23), while designations for multiple signals within a group use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO default to their GPIO functionality. Table 3. MCF5327/8/9 Signal Information and Muxing
MCF5327 196 MAPBGA MCF5328 256 MAPBGA MCF53281 MCF5329 256 MAPBGA Voltage Domain
Signal Name
GPIO
Alternate 1
Alternate 2
Reset RESET2 RSTOUT -- -- -- -- -- -- Clock EXTAL XTAL
2
Dir.1 I O
EVDD EVDD
J11 P14
N15 P14
N15 P14
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
I O I O O
EVDD EVDD EVDD EVDD SDVDD
L14 K14 M11 N11 L1
P16 N16 P13 R13 T2
P16 N16 P13 R13 T2
EXTAL32K XTAL32K FB_CLK
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 6 Freescale Semiconductor
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
MCF5327 196 MAPBGA MCF5328 256 MAPBGA MCF53281 MCF5329 256 MAPBGA Voltage Domain
Signal Name
GPIO
Alternate 1
Alternate 2
Mode Selection RCON
2
-- --
-- --
-- -- FlexBus
Dir.1 I I
EVDD EVDD
M7 G11
M8 H12
M8 H12
DRAMSEL
A[23:22] A[21:16]
-- --
FB_CS[5:4] --
-- --
O O
SDVDD SDVDD
B11,C11 B12, A12, D11, C12, B13, A13 A14, B14 C13, C14, D12 D13 D14, E11-14, F11-F14, G14 H3-H1, J4-J1, K1, L4, M2, M3, N1, N2, P1, P2, N3 F4-F1, G5-G2, L5, N4, P4, M5, N5, P5, L6 M6 M4
C13, D13 E13, A14, B14, C14, A15, B15 D14, B16 C15, C16, D15 D16 E14-E16, F13-F16, G16- G14 M1-M4, N1-N4, T3, P4, R4, T4, N5, P5, R5, T5 J3-J1, K4-K1, L2, R6, N7, P7, R7, T7, P8, R8 T8 L4, P6, L3, N6 R9 G13 N8 H4
C13, D13 E13, A14, B14, C14, A15, B15 D14, B16 C15, C16, D15 D16 E14-E16, F13-F16, G16- G14 M1-M4, N1-N4, T3, P4, R4, T4, N5, P5, R5, T5 J3-J1, K4-K1, L2, R6, N7, P7, R7, T7, P8, R8 T8 L4, P6, L3, N6 R9 G13 N8 H4
A[15:14] A[13:11] A10 A[9:0]
-- -- -- --
SD_BA[1:0]3 SD_A[13:11]3 -- SD_A[9:0]3
-- -- -- --
O O O O
SDVDD SDVDD
SDVDD SDVDD
D[31:16]
--
SD_D[31:16]4
--
I/O
SDVDD
D[15:1]
--
FB_D[31:17]4
--
I/O
SDVDD
D02 BE/BWE[3:0] OE TA2 R/W TS
-- PBE[3:0] PBUSCTL3 PBUSCTL2 PBUSCTL1 PBUSCTL0
FB_D[16]4 SD_DQM[3:0]3 -- -- -- DACK0
-- -- -- -- -- --
I/O O O I O O
SDVDD
SDVDD H4, P3, G1, SDVDD SDVDD SDVDD SDVDD
P6 G13 N6 D2
Chip Selects FB_CS[5:4] FB_CS[3:1] FB_CS0 PCS[5:4] PCS[3:1] -- -- -- -- -- O O O
SDVDD SDVDD
-- A11, D10, C10 B10
B13, A13 A12, B12, C12 D12
B13, A13 A12, B12, C12 D12
SDVDD
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 7
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
MCF5327 196 MAPBGA MCF5328 256 MAPBGA MCF53281 MCF5329 256 MAPBGA Voltage Domain
Signal Name
GPIO
Alternate 1
Alternate 2
SDRAM Controller SD_A10 SD_CKE SD_CLK SD_CLK SD_CS1 SD_CS0 SD_DQS3 SD_DQS2 SD_SCAS SD_SRAS SD_SDR_DQS SD_WE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- O O O O O O O O O O O O
SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD
Dir.1
L2 E1 K3 K2 -- E2 H5 K6 L3 M1 K4 D1
P2 H2 R1 R2 J4 H1 L1 T6 P3 R3 P1 H3
P2 H2 R1 R2 J4 H1 L1 T6 P3 R3 P1 H3
External Interrupts Port5 IRQ72 IRQ62 IRQ52 IRQ42 IRQ32 IRQ22 IRQ12 PIRQ72 PIRQ62 PIRQ52 PIRQ42 PIRQ32 PIRQ22 PIRQ12 -- USBHOST_ VBUS_EN USBHOST_ VBUS_OC SSI_MCLK -- USB_CLKIN DREQ12 -- -- -- -- -- -- SSI_CLKIN FEC FEC_MDC FEC_MDIO FEC_TXCLK FEC_TXEN FEC_TXD0 FEC_COL FEC_RXCLK FEC_RXDV FEC_RXD0 PFECI2C3 PFECI2C2 PFECH7 PFECH6 PFECH5 PFECH4 PFECH3 PFECH2 PFECH1 I2C_SCL2 I2C_SDA2 -- -- ULPI_DATA0 ULPI_CLK ULPI_NXT ULPI_STP ULPI_DATA4 -- -- -- -- -- -- -- -- -- O I/O I O O I I I I
EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD
I I I I I I I
EVDD EVDD
J13 -- -- L13 M14 M13 N13
J13 J14 J15 J16 K14 K15 K16
J13 J14 J15 J16 K14 K15 K16
EVDD
EVDD EVDD EVDD EVDD
-- -- -- -- -- -- -- -- --
C1 C2 A2 B2 E4 A8 C8 D8 C6
C1 C2 A2 B2 E4 A8 C8 D8 C6
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 8 Freescale Semiconductor
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
MCF5327 196 MAPBGA -- -- -- -- -- MCF5328 256 MAPBGA B8 D3-D1 B1 E7, A6, B6 D4 MCF53281 MCF5329 256 MAPBGA B8 D3-D1 B1 E7, A6, B6 D4 Voltage Domain
EVDD EVDD EVDD EVDD EVDD
Signal Name
GPIO
Alternate 1
Alternate 2
FEC_CRS FEC_TXD[3:1] FEC_TXER FEC_RXD[3:1] FEC_RXER
PFECH0 PFECL[7:5] PFECL4 PFECL[3:1] PFECL0
ULPI_DIR ULPI_DATA[3:1] -- ULPI_DATA[7:5] --
-- -- -- -- --
LCD Controller LCD_D17 LCD_D16 LCD_D17 LCD_D16 LCD_D15 LCD_D14 LCD_D13 LCD_D12 LCD_D[11:8] LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D[3:0] LCD_ACD/ LCD_OE LCD_CLS PLCDDH1 PLCDDH0 PLCDDH1 PLCDDH0 PLCDDM7 PLCDDM6 PLCDDM5 PLCDDM4 PLCDDM[3:0] PLCDDL7 PLCDDL6 PLCDDL5 PLCDDL4 PLCDDL[3:0] PLCDCTLH0 PLCDCTLL7 CANTX CANRX -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- O O O O O O O O O O O O O O O O O O O O O O O
EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD
Dir.1 I O O I I
-- -- A6 B6 C6 D6 A5 B5 C5, D5, A4, B4 C4 B3 A3 A2 D4, C3, D3, B2 D7 C7 B7 A7 A8 B8 C8 D8 B9
-- -- C9 D9 A7 B7 C7 D7 D6, E6, A5, B5 C5 D5 A4 A3 B4, C4, B3, C3 B9 A9 D10 C10 B10 A10 A11 B11 C11
C9 D9 -- -- A7 B7 C7 D7 D6, E6, A5, B5 C5 D5 A4 A3 B4, C4, B3, C3 B9 A9 D10 C10 B10 A10 A11 B11 C11
EVDD EVDD EVDD EVDD EVDD
EVDD
EVDD EVDD EVDD
LCD_CONTRAST PLCDCTLL6 LCD_FLM/ LCD_VSYNC LCD_LP/ LCD_HSYNC LCD_LSCLK LCD_PS LCD_REV LCD_SPL_SPR PLCDCTLL5 PLCDCTLL4 PLCDCTLL3 PLCDCTLL2 PLCDCTLL1 PLCDCTLL0
EVDD
EVDD EVDD EVDD EVDD
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 9
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
MCF5327 196 MAPBGA MCF5328 256 MAPBGA MCF53281 MCF5329 256 MAPBGA Voltage Domain
Signal Name
GPIO
Alternate 1
Alternate 2
USB Host & USB On-the-Go USBOTG_M USBOTG_P USBHOST_M USBHOST_P -- -- -- -- -- -- -- -- -- -- -- -- I/O I/O I/O I/O
USB VDD USB VDD USB VDD USB VDD
Dir.1
G12 H13 K13 J12
L15 L16 M15 M16
L15 L16 M15 M16
FlexCAN (MCF53281 & MCF5329 only) CANRX and CANTX do not have dedicated bond pads. Please refer to the following pins for muxing: I2C_SDA, SSI_RXD, or LCD_D16 for CANRX and I2C_SCL, SSI_TXD, or LCD_D17 for CANTX. PWM PWM7 PWM5 PWM3 PWM1 PPWM7 PPWM5 PPWM3 PPWM1 -- -- DT3OUT DT2OUT -- -- DT3IN DT2IN SSI SSI_MCLK SSI_BCLK SSI_FS SSI_RXD2 SSI_TXD2 SSI_RXD
2
I/O I/O I/O I/O
EVDD EVDD EVDD EVDD
-- -- H14 J14
H13 H14 H15 H16
H13 H14 H15 H16
PSSI4 PSSI3 PSSI2 PSSI1 PSSI0 PSSI1 PSSI0
-- U2CTS U2RTS U2RXD U2TXD U2RXD U2TXD
-- PWM7 PWM5 CANRX CANTX -- -- I2C
I/O I/O I/O I O I O
EVDD EVDD EVDD EVDD EVDD EVDD EVDD
-- -- -- -- -- -- --
G4 F4 G3 -- -- G2 G1
G4 F4 G3 G2 G1 -- --
SSI_TXD2
I2C_SCL2 I2C_SDA
2
PFECI2C1 PFECI2C0 PFECI2C1 PFECI2C0
CANTX CANRX -- --
U2TXD U2RXD U2TXD U2RXD DMA
I/O I/O I/O I/O
EVDD EVDD EVDD EVDD
-- -- E3 E4
-- -- F3 F2
F3 F2 -- --
I2C_SCL2 I2C_SDA2
DACK[1:0] and DREQ[1:0] do not have dedicated bond pads. Please refer to the following pins for muxing: TS for DACK0, DT0IN for DREQ0, DT1IN for DACK1, and IRQ1 for DREQ1.
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 10 Freescale Semiconductor
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
MCF5327 196 MAPBGA MCF5328 256 MAPBGA MCF53281 MCF5329 256 MAPBGA Voltage Domain
Signal Name
GPIO
Alternate 1
Alternate 2
QSPI QSPI_CS2 QSPI_CS1 QSPI_CS0 QSPI_CLK QSPI_DIN QSPI_DOUT PQSPI5 PQSPI4 PQSPI3 PQSPI2 PQSPI1 PQSPI0 U2RTS PWM7 PWM5 I2C_SCL U2CTS I2C_SDA
2
-- USBOTG_ PU_EN -- -- -- -- UARTs
Dir.1 O O O O I O
EVDD EVDD
P10 L11 -- N10 L10 M10
T12 T13 P11 R12 N12 P12
T12 T13 P11 R12 N12 P12
EVDD EVDD EVDD EVDD
U1CTS U1RTS U1TXD U1RXD U0CTS U0RTS U0TXD U0RXD
PUARTL7 PUARTL6 PUARTL5 PUARTL4 PUARTL3 PUARTL2 PUARTL1 PUARTL0
SSI_BCLK SSI_FS SSI_TXD2 SSI_RXD2 -- -- -- --
-- -- -- -- -- -- -- --
I O O I I O O I
EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD
C9 D9 A9 A10 P13 N12 P12 P11
D11 E10 E11 E12 R15 T15 T14 R14
D11 E10 E11 E12 R15 T15 T14 R14
Note: The UART2 signals are multiplexed on the QSPI, SSI, DMA Timers, and I2C pins. DMA Timers DT3IN DT2IN DT1IN DT0IN PTIMER3 PTIMER2 PTIMER1 PTIMER0 DT3OUT DT2OUT DT1OUT DT0OUT U2RXD U2TXD DACK1 DREQ02 BDM/JTAG6 JTAG_EN7 DSCLK PSTCLK BKPT DSI DSO DDATA[3:0] -- -- -- -- -- -- -- -- TRST
2
I I I I
EVDD EVDD EVDD EVDD
C1 B1 A1 C2
F1 E1 E2 E3
F1 E1 E2 E3
-- -- -- -- -- -- --
I I O I I O O
EVDD EVDD EVDD EVDD EVDD EVDD EVDD
L12 N14 L7 M12 K12 N9
M13 P15 T9 R16 N14 N11
M13 P15 T9 R16 N14 N11
TCLK2 TMS2 TDI2 TDO --
N7, P7, L8, N9, P9, N10, N9, P9, N10, M8 P10 P10
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 11
Pin Assignments and Reset States
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
MCF5327 196 MAPBGA N8, P8, L9, M9 MCF5328 256 MAPBGA R10, T10, R11, T11 MCF53281 MCF5329 256 MAPBGA R10, T10, R11, T11 Voltage Domain
EVDD
Signal Name
GPIO
Alternate 1
Alternate 2
PST[3:0]
--
--
-- Test
TEST7 PLL_TEST8
-- --
-- --
-- --
Dir.1 O I I
EVDD EVDD
E10 --
A16 N13
A16 N13
Power Supplies EVDD -- -- -- -- -- E6, E7, F5-F7, H9, J8, J9, K8, K9, K11 E8, F5-F8, E8, F5-F8, G5, G6, H5, G5, G6, H5, H6, J11, H6, J11, K11, K12, K11, K12, L9-L11, M9, L9-L11, M9, M10 M10
IVDD PLL_VDD SD_VDD
-- -- --
-- -- --
-- -- --
-- -- --
-- -- --
E5, K5, K10, E5, G12, M5, E5, G12, M5, J10 M11, M12 M11, M12 H10 E8, E9, F8-F10, J5-J7, K7 J12 J12
E9, F9-F11, E9, F9-F11, G11, H11, G11, H11, J5, J6, K5, J5, J6, K5, K6, L5-L8, K6, L5-L8, M6, M7 M6, M7 L14 G7-G10, H7-H10, J7-10, K7-K10, L12, L13 K13 M14 L14 G7-G10, H7-H10, J7-10, K7-K10, L12, L13 K13 M14
USB_VDD VSS
-- --
-- --
-- --
-- --
-- --
G10 G6-G9, H6-H8, P9
PLL_VSS USB_VSS
1 2 3 4 5 6 7 8
-- --
-- --
-- --
-- --
-- --
H11 H12
Refers to pin's primary function. Pull-up enabled internally on this signal for this mode. The SDRAM functions of these signals are not programmable by the user. They are dynamically switched by the processor when accessing SDRAM memory space and are included here for completeness. Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins. GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions. If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins. Pull-down enabled internally on this signal for this mode. Must be left floating for proper operation of the PLL.
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 12 Freescale Semiconductor
Pin Assignments and Reset States
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 13
Pin Assignments and Reset States
NOTE
4.2
Pinout--256 MAPBGA
NOTE
The pin at location N13 (PLL_TEST) must be left floating or improper operation of the PLL module occurs.
Figure 4 shows a pinout of the MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 devices.
1 A NC FEC_ TXER FEC_ MDC FEC_ TXD1 DT2IN
2 FEC_ TXCLK FEC_ TXEN FEC_ MDIO FEC_ TXD2 DT1IN I2C_ SDA SSI_ RXD SD_CKE
3 LCD_ D4 LCD_ D1 LCD_ D0 FEC_ TXD3 DT0IN I2C_ SCL SSI_FS
4 LCD_ D5 LCD_ D3 LCD_ D2 FEC_ RXER FEC_ TXD0 SSI_ BCLK SSI_ MCLK TS
5 LCD_ D9 LCD_ D8 LCD_ D7 LCD_ D6 IVDD
6 FEC_ RXD2 FEC_ RXD1 FEC_ RXD0 LCD_ D11 LCD_ D10 EVDD
7 LCD_ D15 LCD_ D14 LCD_ D13 LCD_ D12 FEC_ RXD3 EVDD
8 FEC_ COL FEC_ CRS FEC_ RXCLK FEC_ RXDV EVDD
9 LCD_ CLS LCD_ ACD/OE LCD_ D17 LCD_ D16 SD_VDD
10 LCD_ LSCLK LCD_LP/ HSYNC LCD_FLM/ VSYNC LCD_CON TRAST U1RTS
11 LCD_ PS LCD_ REV LCD_ SPL_SPR U1CTS
12
13
14 A20
15 A17
16 TEST A
FB_CS3 FB_CS4
B
FB_CS2 FB_CS5
A19
A16
A14
B
C
FB_CS1
A23
A18
A13
A12
C
D
FB_CS0
A22
A15
A11
A10
D
E
U1TXD
U1RXD
A21
A9
A8
A7
E
F
DT3IN
EVDD
EVDD
SD_VDD
SD_VDD
SD_VDD
NC
A6
A5
A4
A3
F
G
SSI_ TXD SD_ CS0
EVDD
EVDD
VSS
VSS
VSS
VSS
SD_VDD
IVDD DRAM SEL PLL_ VDD EVDD
TA
A0
A1
A2
G
H
SD_WE
EVDD
EVDD
VSS
VSS
VSS
VSS
SD_VDD
PWM7
PWM5
PWM3
PWM1
H
J
D13
D14
D15
SD_CS1 SD_VDD SD_VDD
VSS
VSS
VSS
VSS
EVDD
IRQ7 PLL_ VSS USB_ VSS JTAG_ EN PLL_ TEST EXTAL 32K XTAL 32K QSPI_ CS1 13
IRQ6
IRQ5
IRQ4
J
K
D9 SD_ DQS3 D31
D10
D11 BE/ BWE1
D12 BE/ BWE3
SD_VDD SD_VDD
VSS
VSS
VSS
VSS
EVDD
IRQ3 USBOTG _VDD USBHOST _VSS TDI/DSI
IRQ2 USB OTG_M USB
IRQ1 USB OTG_P USB
K
L
D8
SD_VDD SD_VDD SD_VDD SD_VDD
EVDD
EVDD
EVDD
VSS
L
M
D30
D29
D28
IVDD
SD_VDD SD_VDD
RCON
EVDD
EVDD
IVDD TDO/ DSO QSPI_ CS0 PST1
IVDD QSPI_ DIN QSPI_ DOUT QSPI_ CLK QSPI_ CS2 12
HOST_M HOST_P RESET XTAL
M
N
D27 SD_DR _DQS
D26
D25
D24
D19
BE/ BWE0 BE/ BWE2
D6
R/W
DDATA3
DDATA1
N
P
SD_A10
SD_CAS
D22
D18
D5
D2
DDATA2
DDATA0
RSTOUT
TRST/ DSCLK
EXTAL
P
R SD_CLK SD_CLK
SD_RAS
D21
D17
D7 SD_ DQS2 6
D4
D1
OE TCLK/ PSTCLK 9
PST3
U0RXD
U0CTS
TMS/ BKPT
R
T
NC 1
FB_CLK 2
D23 3
D20 4
D16 5
D3 7
D0 8
PST2 10
PST0 11
U0TXD 14
U0RTS
NC 16
T
15
Figure 4. MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 Pinout Top View (256 MAPBGA)
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 14 Freescale Semiconductor
Electrical Characteristics
4.3
1 A DT1IN
Pinout--196 MAPBGA
2 LCD_ D4 LCD_ D0 3 LCD_ D5 LCD_ D6 LCD_ D2 LCD_ D1 4 LCD_ D9 LCD_ D8 LCD_ D7 LCD_ D3 5 LCD_ D13 LCD_ D12 LCD_ D11 LCD_ D10 6 LCD_ D17 LCD_ D16 LCD_ D15 LCD_ D14 7 8 9 U1TXD 10 U1RXD 11 FB_CS3 12 A20 13 A16 14 A15 A
The pinout for the MCF5327CVM240 package is shown below.
LCD_FLM/ LCD_LP/ VSYNC HSYNC LCD_CON TRAST LCD_ CLS LCD_ ACD/OE LCD_ LSCLK LCD_ PS LCD_ REV
B
D2TIN
LCD_ SPL_SPR
FB_CS0
A23
A21
A17
A14
B
C
DT3IN
DT0IN
U1CTS
FB_CS1
A22
A18
A13
A12
C
D
SD_WE
TS
U1RTS
FB_CS2
A19
A11
A10
A9
D
E
SD_CKE SD_CS0
I2C_SCL I2C_SDA
IVDD
EVDD
EVDD
SD_VDD SD_VDD
TEST
A8
A7
A6
A5
E
F
D12
D13
D14
D15
EVDD
EVDD
EVDD
SD_VDD SD_VDD
SD_VDD
A4
A3
A2
A1
F
G
BE/ BWE1
D8
D9
D10
D11
VSS
VSS
VSS
VSS
USB OTG_VDD PLL_ VDD
DRAM SEL PLL_ VSS
USB OTG_M USBHOST _VSS USB HOST_P
TA
A0
G
H
D29
D30
D31
BE/ BWE3
SD_ DQS3
VSS
VSS
VSS
EVDD
USB OTG_P
PWM3
H
J
D25
D26
D27
D28
SD_VDD SD_VDD
SD_VDD
EVDD
EVDD
IVDD
RESET
IRQ7
PWM1
J
K
D24
SD_CLK
SD_CLK
SD_DR_ DQS
IVDD
SD_ DQS2
SD_VDD
EVDD
EVDD
IVDD
EVDD
TDI/DSI
USB HOST_M
XTAL
K
L
FB_CLK SD_A10
SD_CAS
D23
D7
D1
TCLK/ PSTCLK
DDATA1
PST1
QSPI_ DIN QSPI_ DOUT QSPI_ CLK QSPI_ CS2 10
QSPI_ CS1 EXTAL 32K XTAL 32K
JTAG_ EN TMS/ BKPT
IRQ4
EXTAL
L
M
SD_RAS
D22
D21
BE/ BWE0
D4
D0
RCON
DDATA0
PST0
IRQ2
IRQ3
M
N
D20
D19
D16
D6
D3
R/W
DDATA3
PST3
TDO/ DSO
U0RTS
IRQ1
TRST/ DSCLK
N
P
D18 1
D17 2
BE/ BWE2 3
D5 4
D2 5
OE 6
DDATA2 7
PST2 8
VSS 9
U0RXD 11
U0TXD 12
U0CTS 13
RSTOUT 14
P
Figure 5. MCF5327CVM240 Pinout Top View (196 MAPBGA)
5
Electrical Characteristics
This document contains electrical specification tables and reference timing diagrams for the MCF5329 microcontroller unit. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of MCF5329. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. However, for production silicon, these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed.
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 15
Electrical Characteristics
NOTE
The parameters specified in this MCU document supersede any values found in the module specifications.
5.1
Maximum Ratings
Table 4. Absolute Maximum Ratings1, 2
Rating Core Supply Voltage CMOS Pad Supply Voltage DDR/Memory Pad Supply Voltage PLL Supply Voltage Digital Input Voltage
3
Symbol IVDD EVDD SDVDD PLLVDD VIN ID TA (TL - TH) Tstg
Value - 0.5 to +2.0 - 0.3 to +4.0 - 0.3 to +4.0 - 0.3 to +2.0 - 0.3 to +3.6 25 - 40 to +85 - 55 to +150
Unit V V V V V mA C C
Instantaneous Maximum Current Single pin limit (applies to all pins) 3, 4, 5 Operating Temperature Range (Packaged) Storage Temperature Range
1
2
3
4 5
Functional operating conditions are given in Section 5.4, "DC Electrical Specifications." Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Continued operation at these levels may affect device reliability or cause permanent damage to the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (VSS or EVDD). Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, and then use the larger of the two values. All functional non-supply pins are internally clamped to VSS and EVDD. Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > EVDD) is greater than IDD, the injection current may flow out of EVDD and could result in external power supply going out of regulation. Ensure external EVDD load shunts current greater than maximum injection current. This is the greatest risk when the MCU is not consuming power (ex; no clock). Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum current conditions.
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 16 Freescale Semiconductor
Electrical Characteristics
5.2
Thermal Characteristics
Table 5. Thermal Characteristics
Characteristic Junction to ambient, natural convection Junction to ambient (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature
1
Symbol Four layer board (2s2p) Four layer board (2s2p) -- -- -- -- JMA JMA JB JC jt Tj
256MBGA 371,2 341,2 273 164 41,5 105
196MBGA 421,2 381,2 323 194 51,5 105
Unit C/W C/W C/W C/W C/W
o
C
2 3 4 5
JMA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of JmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT.
The average chip-junction temperature (TJ) in C can be obtained from:
T J = T A + ( P D x JMA )
Eqn. 1
Where:
TA QJMA PD PINT PI/O = = = = = Ambient Temperature, C Package Thermal Resistance, Junction-to-Ambient, C/W PINT + PI/O IDD x IVDD, Watts - Chip Internal Power Power Dissipation on Input and Output Pins -- User Determined
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:
K P D = -------------------------------( T J + 273C )
Eqn. 2
Solving equations 1 and 2 for K gives: K = P D x ( T A x 273C ) + Q JMA x P D
2
Eqn. 3
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 17
Electrical Characteristics
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA.
5.3
ESD Protection
Table 6. ESD Protection Characteristics1, 2
Characteristics ESD Target for Human Body Model
1
Symbol HBM
Value 2000
Units V
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
5.4
DC Electrical Specifications
Table 7. DC Electrical Specifications
Characteristic Symbol IVDD PLLVDD EVDD SDVDD 1.70 2.25 3.0 USBVDD EVIH EVIL EVOH EVOL SDVIH 1.35 1.7 2 SDVIL VSS - 0.3 VSS - 0.3 VSS - 0.3 0.45 0.8 0.8 3.0 2 VSS - 0.3 EVDD - 0.4 -- 1.95 2.75 3.6 3.6 EVDD + 0.3 0.8 -- 0.4 V V V V V V SDVDD + 0.3 SDVDD + 0.3 SDVDD + 0.3 V Min 1.4 1.4 3.0 Max 1.6 1.6 3.6 Unit V V V V
Core Supply Voltage PLL Supply Voltage CMOS Pad Supply Voltage SDRAM and FlexBus Supply Voltage Mobile DDR/Bus Pad Supply Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) USB Supply Voltage CMOS Input High Voltage CMOS Input Low Voltage CMOS Output High Voltage IOH = -5.0 mA CMOS Output Low Voltage IOL = 5.0 mA SDRAM and FlexBus Input High Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) SDRAM and FlexBus Input Low Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V)
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 18 Freescale Semiconductor
Electrical Characteristics
Table 7. DC Electrical Specifications (continued)
Characteristic SDRAM and FlexBus Output High Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) IOH = -5.0 mA for all modes SDRAM and FlexBus Output Low Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) IOL = 5.0 mA for all modes Input Leakage Current Vin = VDD or VSS, Input-only pins Weak Internal Pull-Up Device Current, tested at VIL Max.1 Input Capacitance 2 All input-only pins All input/output (three-state) pins
1 2
Symbol SDVOH
Min SDVDD - 0.35 2.1 2.4
Max -- -- --
Unit V
SDVOL -- -- -- Iin IAPU Cin -- -- 7 7 -1.0 -10 0.3 0.3 0.5 1.0 -130
V
A A pF
Refer to the signals section for pins having weak internal pull-up devices. This parameter is characterized before qualification rather than 100% tested.
5.5
Oscillator and PLL Electrical Characteristics
Table 8. PLL Electrical Characteristics
Num
Characteristic PLL Reference Frequency Range Crystal reference External reference Core frequency CLKOUT Frequency2 Crystal Start-up Time3, 4 EXTAL Input High Voltage Crystal Mode5 All other modes (External, Limp) EXTAL Input Low Voltage Crystal Mode5 All other modes (External, Limp) PLL Lock Time 3, 6 Duty Cycle of reference XTAL Current Total on-chip stray capacitance on XTAL Total on-chip stray capacitance on EXTAL
3
Symbol
Min. Value 12 12 488 x 10-6 163 x 10-6 -- VXTAL + 0.4 EVDD/2 + 0.4 -- -- -- 40 1
Max. Value 251 401 240 80 10 -- -- VXTAL - 0.4 EVDD/2 - 0.4 50000 60 3 1.5 1.5
Unit
1
fref_crystal fref_ext fsys fsys/3 tcst VIHEXT VIHEXT VILEXT VILEXT tlpll tdc IXTAL CS_XTAL CS_EXTAL
MHz MHz MHz MHz ms V V V V CLKIN % mA pF pF
2 3 4
5 7 8 9 10 11
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 19
Electrical Characteristics
Table 8. PLL Electrical Characteristics (continued)
Num 12 Characteristic Crystal capacitive load Discrete load capacitance for XTAL 13 Discrete load capacitance for EXTAL 14 CLKOUT Period Jitter, 3, 4, 7, 8, 9 Measured at fSYS Max Peak-to-peak Jitter (Clock edge to clock edge) Long Term Jitter Frequency Modulation Range Limit 3, 10, 11 (fsysMax must not be exceeded) VCO Frequency. fvco = (fref * PFD)/4 Cjitter -- -- Cmod fvco 0.8 350 10 TBD 2.2 540 % fsys/3 % fsys/3 %fsys/3 MHz CL_EXTAL Symbol CL CL_XTAL Min. Value Max. Value See crystal spec 2*CL - CS_XTAL - CPCB_XTAL7 2*CL-CS_EXTAL - CPCB_EXTAL7 pF Unit
pF
17
18 19
1
The maximum allowable input clock frequency when booting with the PLL enabled is 24MHz. For higher input clock frequencies the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency. 2 All internal registers retain data at 0 Hz. 3 This parameter is guaranteed by characterization before qualification rather than 100% tested. 4 Proper PC board layout procedures must be followed to achieve specifications. 5 This parameter is guaranteed by design rather than 100% tested. 6 This specification is the PLL lock time only and does not include oscillator start-up time. 7C PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively. 8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f sys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval. 9 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod. 10 Modulation percentage applies over an interval of 10 s, or equivalently the modulation rate is 100 KHz. 11 Modulation range determined by hardware design.
5.6
External Interface Timing Characteristics
NOTE
All processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. The reference clock is the FB_CLK output. All other timing relationships can be derived from these values. Timings listed in Table 9 are shown in Figure 7 and Figure 8.
Table 9 lists processor bus input timings.
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 20 Freescale Semiconductor
Electrical Characteristics
* The timings are also valid for inputs sampled on the negative clock edge. FB_CLK (80MHz) TSETUP THOLD 1.5V
Input Setup And Hold
Invalid
1.5V Valid 1.5V
Invalid
trise Input Rise Time Vh = VIH Vl = VIL tfall Input Fall Time Vh = VIH Vl = VIL
FB_CLK
B4 B5
Inputs
Figure 6. General Input Timing Requirements
5.6.1
FlexBus
A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple chip-select based interface can be used. The FlexBus interface has six general purpose chip-selects (FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory interfaces. Chip-select, FB_CS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM/flash memories.
5.6.1.1
FlexBus AC Timing Characteristics
Table 9. FlexBus AC Timing Specifications
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the system clock.
Num -- FB1 FB2 FB3 Frequency of Operation Clock Period (FB_CLK)
Characteristic
Symbol fsys/3 tFBCK (tcyc) tFBCHDCV tFBCHDCI
Min -- 12.5 -- 1
Max 80 -- 7.0 --
Unit Mhz ns ns ns
Address, Data, and Control Output Valid (A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)1 Address, Data, and Control Output Hold (A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)1, 2
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 21
Electrical Characteristics
Table 9. FlexBus AC Timing Specifications (continued)
Num FB4 FB5 FB6 FB7
1
Characteristic Data Input Setup Data Input Hold Transfer Acknowledge (TA) Input Setup Transfer Acknowledge (TA) Input Hold
Symbol tDVFBCH tDIFBCH tCVFBCH tCIFBCH
Min 3.5 0 4 0
Max -- -- -- --
Unit ns ns ns ns
Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2, "DDR SDRAM AC Timing Characteristics" for SD_CS[3:0] timing. 2 The FlexBus supports programming an extension of the address hold. Please consult the Reference Manual for more information.
NOTE The processor drives the data lines during the first clock cycle of the transfer with the full 32-bit address. This may be ignored by standard connected devices using non-multiplexed address and data buses. However, some applications may find this feature beneficial. The address and data busses are muxed between the FlexBus and SDRAM controller. At the end of the read and write bus cycles the address signals are indeterminate.
S0 S1 S2 S3
FB_CLK
FB1 FB3 ADDR[23:0] FB2 ADDR[31:X] DATA FB4 FB5
FB_A[23:0] FB_D[31:X]
FB_R/W FB_TS FB_CSn, FB_OE, FB_BE/BWEn
FB6 FB7
FB_TA
Figure 7. FlexBus Read Timing
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 22 Freescale Semiconductor
Electrical Characteristics
S0 S1 S2 S3
FB_CLK
FB1 FB3 ADDR[23:0] FB2
FB_A[23:0]
FB_D[31:X] FB_R/W FB_TS FB_CSn, FB_BE/BWEn FB_OE FB_TA
ADDR[31:X]
DATA
FB6 FB7
Figure 8. FlexBus Write Timing
5.7
SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
5.7.1
SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device's SDRAM controller is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must remain supplied to the device for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the SD_SDR_DQS signal and its usage. Table 10. SDR Timing Specifications
Symbol * SD1 SD3 SD4 SD5 SD6 SD7 SD8 Characteristic Frequency of Operation1 Clock Period Pulse Width
2
Symbol * tSDCK tSDCKH tSDCKH tSDCHACV tSDCHACI tDQSOV
6
Min TBD 12.5 0.45 0.45 -- 2.0 -- 0.25 x SD_CLK
Max 80 TBD 0.55 0.55 0.5 x SD_CLK + 1.0 -- Self timed 0.40 x SD_CLK
Unit MHz ns SD_CLK SD_CLK ns ns ns ns
High3
Pulse Width Low4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Valid Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Hold SD_SDR_DQS Output Valid5 SD_DQS[3:0] input setup relative to SD_CLK
tDQVSDCH
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 23
Electrical Characteristics
Table 10. SDR Timing Specifications (continued)
Symbol SD9 SD10 SD11 SD12 SD13
1 2 3 4 5 6 7 8
Characteristic SD_DQS[3:2] input hold relative to SD_CLK7 Data (D[31:0]) Input Setup relative to SD_CLK (reference only)8 Data Input Hold relative to SD_CLK (reference only) Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold
Symbol
Min
Max
Unit
tDQISDCH Does not apply. 0.5xSD_CLK fixed width. tDVSDCH tDISDCH tSDCHDMV tSDCHDMI 0.25 x SD_CLK 1.0 -- 1.5 -- -- 0.75 x SD_CLK + 0.5 -- ns ns ns ns
The FlexBus and SDRAM clock operates at the same frequency of the internal bus clock. See the PLL chapter of the MCF5329 Reference Manual for more information on setting the SDRAM clock rate. SD_CLK is one SDRAM clock in (ns). Pulse width high plus pulse width low cannot exceed min and max clock period. Pulse width high plus pulse width low cannot exceed min and max clock period. SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation from this guideline is expected. SD_DQS only pulses during a read cycle and one pulse occurs for each data beat. SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat. The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does not affect the memory controller. Because a read cycle in SDR mode uses the DQS circuit within the device, it is most critical that the data valid window be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup spec is provided as guidance.
SD1 SD_CLK
SD2
SD3 SD5 SD_CSn SD_RAS SD_CAS SD_WE A[23:0] SD_BA[1:0]
CMD
SD4
ROW
COL
SD11
SDDM SD12 D[31:0]
WD1
WD2
WD3
WD4
Figure 9. SDR Write Timing
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 24 Freescale Semiconductor
Electrical Characteristics
SD1 SD_CLK SD_CSn, SD_RAS, SD_CAS, SD_WE A[23:0], SD_BA[1:0] SD5 SD3 SD2
CMD
SD4
3/4 MCLK Reference
ROW
COL
tDQS
SDDM SD6 SD_SDR_DQS
(Measured at Output Pin) Board Delay
SD8
SD_DQS[3:2]
(Measured at Input Pin) Board Delay
SD7
Delayed SD_CLK SD9 D[31:0] from Memories
WD1 WD2 WD3 WD4
NOTE: Data driven from memories relative to delayed memory clock.
SD10
Figure 10. SDR Read Timing
5.7.2
DDR SDRAM AC Timing Characteristics
When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte lanes. Table 11. DDR Timing Specifications
Num * DD1 DD2 DD3 DD4 DD5 DD6 DD7 Characteristic Frequency of Operation Clock Period
1 2
Symbol tDDCK tDDSK tDDCKH tDDCKL tSDCHACV tSDCHACI tCMDVDQ tDQDMV
Min TBD 12.5 0.45 0.45 -- 2.0 -- 1.5
Max 80 TBD 0.55 0.55 0.5 x SD_CLK + 1.0 -- 1.25 --
Unit Mhz ns SD_CLK SD_CLK ns ns SD_CLK ns
Pulse Width High
Pulse Width Low3 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] - Output Valid3 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] - Output Hold Write Command to first DQS Latching Transition Data and Data Mask Output Setup (DQ-->DQS) Relative to DQS (DDR Write Mode)4, 5
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 25
Electrical Characteristics
Table 11. DDR Timing Specifications (continued)
Num DD8 DD9 DD10 Characteristic Data and Data Mask Output Hold (DQS-->DQ) Relative to DQS (DDR Write Mode)6 Input Data Skew Relative to DQS (Input Setup)7 Input Data Hold Relative to DQS
8
Symbol tDQDMI tDVDQ tDIDQ tDQLSDCH tDQRPRE tDQRPST tDQWPRE tDQWPST
Min 1.0 -- 0.25 x SD_CLK + 0.5ns 0.5 0.9 0.4 0.25 0.4
Max -- 1 -- -- 1.1 0.6
Unit ns ns ns ns SD_CLK SD_CLK SD_CLK
DD11 DQS falling edge from SDCLK rising (output hold time) DD12 DQS input read preamble width DD13 DQS input read postamble width DD14 DQS output write preamble width DD15 DQS output write postamble width
1 2 3 4
0.6
SD_CLK
5 6
7
8
SD_CLK is one SDRAM clock in (ns). Pulse width high plus pulse width low cannot exceed min and max clock period. Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature, and voltage variations. This specification relates to the required input setup time of today's DDR memories. The processor's output setup should be larger than the input setup of the DDR memories. If it is not larger, the input setup on the memory is in violation. MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0]. The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are valid for each subsequent DQS edge. This specification relates to the required hold time of today's DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0]. Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes invalid.
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 26 Freescale Semiconductor
Electrical Characteristics
DD1 SD_CLK
DD2
DD3 SD_CLK
DD5 SD_CSn,SD_WE, SD_RAS, SD_CAS DD4 A[13:0]
CMD
DD6
ROW
COL
DD7
DM3/DM2 DD8 SD_DQS3/SD_DQS2 DD7 D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
DD8
Figure 11. DDR Write Timing
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 27
Electrical Characteristics
DD1 SD_CLK
DD2
DD3 SD_CLK
DD5 SD_CSn,SD_WE, SD_RAS, SD_CAS DD4 A[13:0]
CL=2
CMD CL=2.5 ROW COL DQS Read Preamble
DD10 DD9
SD_DQS3/SD_DQS2 CL = 2
DQS Read Postamble
D[31:24]/D[23:16]
SD_DQS3/SD_DQS2 CL = 2.5
WD1 WD2 WD3 WD4 DQS Read DQS Read Preamble Postamble
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
Figure 12. DDR Read Timing
5.8
Num G1 G2 G3 G4
1
General Purpose I/O Timing
Table 12. GPIO Timing1
Characteristic FB_CLK High to GPIO Output Valid FB_CLK High to GPIO Output Invalid GPIO Input Valid to FB_CLK High FB_CLK High to GPIO Input Invalid Symbol tCHPOV tCHPOI tPVCH tCHPI Min -- 1.5 9 1.5 Max 10 -- -- -- Unit ns ns ns ns
GPIO pins include: IRQn, PWM, UART, FlexCAN, and Timer pins.
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 28 Freescale Semiconductor
Electrical Characteristics
FB_CLK
G1
GPIO Outputs
G2
G3
GPIO Inputs
G4
Figure 13. GPIO Timing
5.9
Num R1 R2 R3 R4 R5 R6 R7 R8
1
Reset and Configuration Override Timing
Table 13. Reset and Configuration Override Timing
Characteristic RESET Input valid to FB_CLK High FB_CLK High to RESET Input invalid RESET Input valid Time
1
Symbol tRVCH tCHRI tRIVT tCHROV tROVCV tCOS tCOH tROICZ
Min 9 1.5 5 -- 0 20 0 --
Max -- -- -- 10 -- -- -- 1
Unit ns ns tCYC ns ns tCYC ns tCYC
FB_CLK High to RSTOUT Valid RSTOUT valid to Config. Overrides valid Configuration Override Setup Time to RSTOUT invalid Configuration Override Hold Time after RSTOUT invalid RSTOUT invalid to Configuration Override High Impedance
During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns.
FB_CLK
R1 R3
RESET
R2
R4
RSTOUT
R4 R8 R5 R6 R7
Configuration Overrides*: (RCON, Override pins])
Figure 14. RESET and Configuration Override Timing
NOTE
Refer to the CCM chapter of the MCF5329 Reference Manual for more information.
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 29
Electrical Characteristics
5.10
LCD Controller Timing Specifications
Table 14. LCD_LSCLK Timing
Num T1 T2 T3 Parameter LCD_LSCLK Period Pixel data setup time Pixel data up time Minimum 25 11 11 Maximum 2000 -- -- Unit ns ns ns
This sections lists the timing specifications for the LCD Controller.
Note: The pixel clock is equal to LCD_LSCLK / (PCD + 1). When it is in CSTN, TFT or monochrome mode with bus width is set and LCD_LSCLK is equal to the pixel clock. When it is in monochrome with other bus width settings, LCD_LSCLK is equal to the pixel clock divided by bus width. The polarity of LCD_LSCLK and LCD_LD signals can also be programmed.
T1 LCD_LSCLK
LCD_LD[17:0] T2 T3
Figure 15. LCD_LSCLK to LCD_LD[17:0] timing diagram
Non-display region
T1 T3
Display region
T4
LCD_VSYNC LCD_HSYNC LCD_OE LCD_LD[17:0]
T2
Line Y
Line 1
Line Y
T5 LCD_HSYNC LCD_LSCLK LCD_OE LCD_LD[15:0]
T6
XMAX
T7
(1,1)
(1,2)
(1,X)
Figure 16. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 30 Freescale Semiconductor
Electrical Characteristics
Table 15. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing
Number T1 T2 T3 T4 T5 T6 T7 Description End of LCD_OE to beginning of LCD_VSYNC LCD_HSYNC period LCD_VSYNC pulse width End of LCD_VSYNC to beginning of LCD_OE LCD_HSYNC pulse width End of LCD_HSYNC to beginning to LCD_OE End of LCD_OE to beginning of LCD_HSYNC Minimum T5+T6+T7-1 -- T2 1 1 3 1 Value (VWAIT1*T2)+T5+T6+T7-1 XMAX+T5+T6+T7 VWIDTH*T2 (VWAIT2*T2)+1 HWIDTH+1 HWAIT2+3 HWAIT1+1 Unit Ts Ts Ts Ts Ts Ts Ts
Note: Ts is the LCD_LSCLK period. LCD_VSYNC, LCD_HSYNC and LCD_OE can be programmed as active high or active low. In Figure 16, all 3 signals are active low. LCD_LSCLK can be programmed to be deactivated during the LCD_VSYNC pulse or the LCD_OE deasserted period. In Figure 16, LCD_LSCLK is always active. Note: XMAX is defined in number of pixels in one line.
XMAX
LCD_LSCLK
LCD_LD
D320
D1
D2
D320
LCD_SPL_SPR
T1
LCD_HSYNC
T2
T3
T2
LCD_CLS LCD_PS T7 LCD_REV
T4 T5 T6
T4
T7
Figure 17. Sharp TFT Panel Timing
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 31
Electrical Characteristics
Table 16. Sharp TFT Panel Timing
Num T1 T2 T3 T4 T5 T6 T7 Description LCD_SPL/LCD_SPR pulse width End of LCD_LD of line to beginning of LCD_HSYNC End of LCD_HSYNC to beginning of LCD_LD of line LCD_CLS rise delay from end of LCD_LD of line LCD_CLS pulse width LCD_PS rise delay from LCD_CLS negation LCD_REV toggle delay from last LCD_LD of line Minimum -- 1 4 3 1 0 1 Value 1 HWAIT1+1 HWAIT2 + 4 CLS_RISE_DELAY+1 CLS_HI_WIDTH+1 PS_RISE_DELAY REV_TOGGLE_DELAY+1 Unit Ts Ts Ts Ts Ts Ts Ts
Note: Falling of LCD_SPL/LCD_SPR aligns with first LCD_LD of line. Note: Falling of LCD_PS aligns with rising edge of LCD_CLS. Note: LCD_REV toggles in every LCD_HSYN period.
T1
T1
LCD_VSYNC
T2 LCD_HSYNC LCD_LSCLK
T3
XMAX
T4
T2
Ts LCD_LD[15:0]
Figure 18. Non-TFT Mode Panel Timing Table 17. Non-TFT Mode Panel Timing
Num T1 T2 T3 T4 Description LCD_HSYNC to LCD_VSYNC delay LCD_HSYNC pulse width LCD_VSYNC to LCD_LSCLK LCD_LSCLK to LCD_HSYNC Minimum 2 1 -- 1 Value HWAIT2 + 2 HWIDTH + 1 0 T3 Ts HWAIT1 + 1 Unit Tpix Tpix -- Tpix
Note: Ts is the LCD_LSCLK period while Tpix is the pixel clock period. LCD_VSYNC, LCD_HSYNC and LCD_LSCLK can be programmed as active high or active low. In Figure 18, all three signals are active high. When it is in CSTN mode or monochrome mode with bus width = 1, T3 = Tpix = Ts. When it is in monochrome mode with bus width = 2, 4 and 8, T3 = 1, 2 and 4 Tpix respectively.
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 32 Freescale Semiconductor
Electrical Characteristics
5.11 5.12
USB On-The-Go ULPI Timing Specification
The MCF5329 device is compliant with industry standard USB 2.0 specification.
Control and data timing requirements for the ULPI pins are given in Table 18. These timings apply in synchronous mode only. All timings are measured with either a 60 MHz input clock from the USB_CLKIN pin. The USB_CLKIN needs to maintain a 50% duty cycle. Control signals and 8-bit data are always clocked on the rising edge. The ULPI interface on the MCF5329 processor is compliant with the industry standard definition.
THD TSD THC TDD TDC
TSC
ULPI_CLK ULPI_STP (Input) ULPI_DATA (Input-8bit) ULPI_DIR/ULPI_NXT (Output) ULPI_DATA (Output-8bit)
Figure 19. ULPI Timing Diagram Table 18. ULPI Interface Timing
Parameter Setup time (control in, 8-bit data in) Hold time (control in, 8-bit data in) Output delay (control out, 8-bit data out) Symbol TSC, TSD THC, THD TDC, TDD Min -- -1.5 -- Max 3.0 -- 6.0 Units ns ns ns
5.13
SSI Timing Specifications
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync (SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below. Table 19. SSI Timing - Master Modes1
Num S1 S2 S3 S4 S5 Description SSI_MCLK cycle time
2
Symbol tMCLK
Min 8 x tSYS 45% 8 x tSYS 45% --
Max -- 55% -- 55% 15
Units ns tMCLK ns tBCLK ns
SSI_MCLK pulse width high / low SSI_BCLK cycle time
3
tBCLK
SSI_BCLK pulse width SSI_BCLK to SSI_FS output valid
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 33
Electrical Characteristics
Table 19. SSI Timing - Master Modes1 (continued)
Num S6 S7 S8 S9 S10
1 2
Description SSI_BCLK to SSI_FS output invalid SSI_BCLK to SSI_TXD valid SSI_BCLK to SSI_TXD invalid / high impedence SSI_RXD / SSI_FS input setup before SSI_BCLK SSI_RXD / SSI_FS input hold after SSI_BCLK
Symbol
Min -2 -- -4 15 0
Max -- 15 -- -- --
Units ns ns ns ns ns
All timings specified with a capactive load of 25pF. SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (SYSCLK). 3 SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the minimum divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure that SSI_BCLK does not exceed 4 x fSYS.
Table 20. SSI Timing - Slave Modes1
Num S11 S12 S13 S14 S15 S16 S17 S18
1
Description SSI_BCLK cycle time SSI_BCLK pulse width high/low SSI_FS input setup before SSI_BCLK SSI_FS input hold after SSI_BCLK SSI_BCLK to SSI_TXD/SSI_FS output valid SSI_BCLK to SSI_TXD/SSI_FS output invalid/high impedence SSI_RXD setup before SSI_BCLK SSI_RXD hold after SSI_BCLK
Symbol tBCLK
Min 8 x tSYS 45% 10 3 -- -2 10 3
Max -- 55% -- -- 15 -- -- --
Units ns tBCLK ns ns ns ns ns ns
All timings specified with a capactive load of 25pF.
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 34 Freescale Semiconductor
Electrical Characteristics
S1
S2
S2
SSI_MCLK (Output)
S3
SSI_BCLK (Output)
S5
S4
S4 S6
SSI_FS (Output)
S9 S10 S7 S7 S8 S8
SSI_FS (Input)
SSI_TXD
S9 S10
SSI_RXD
Figure 20. SSI Timing - Master Modes
S11
SSI_BCLK (Input)
S15
S12 S12 S16
SSI_FS (Output)
S13
SSI_FS (Input)
S15
S14 S15 S16 S16
SSI_TXD
S17 S18
SSI_RXD
Figure 21. SSI Timing - Slave Modes
5.14
I2C Input/Output Timing Specifications
Table 21. I2C Input Timing Specifications between SCL and SDA
Num I1 I2 I3 I4 Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time Min 2 8 -- 0 Max -- -- 1 -- Units tcyc tcyc ms ns
Table 21 lists specifications for the I2C input timing parameters shown in Figure 22.
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 35
Electrical Characteristics
Table 21. I2C Input Timing Specifications between SCL and SDA (continued)
Num I5 I6 I7 I8 I9 Characteristic I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min -- 4 0 2 2 Max 1 -- -- -- -- Units ms tcyc ns tcyc tcyc
Table 22 lists specifications for the I2C output timing parameters shown in Figure 22. Table 22. I2C Output Timing Specifications between SCL and SDA
Num I11 I2 1 I3
2
Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time
Min 6 10 -- 7 -- 10 2 20 10
Max -- -- -- -- 3 -- -- -- --
Units tcyc tcyc s tcyc ns tcyc tcyc tcyc tcyc
I4 1 I5 3 I6 I7 I8
1 1 1
I9 1
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 22. The I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 22 are minimum values. 2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load.
Figure 22 shows timing for the values in Table 22 and Table 21.
I5 I2 I2C_SCL I1 I2C_SDA I4 I7 I8 I9 I6
I3
Figure 22. I2C Input/Output Timings
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 36 Freescale Semiconductor
Electrical Characteristics
5.15
Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V.
5.15.1
MII Receive Signal Timing
The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. The processor clock frequency must exceed twice the FEC_RXCLK frequency. Table 23 lists MII receive channel timings. Table 23. MII Receive Signal Timing
Num M1 M2 M3 M4 Characteristic FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold FEC_RXCLK pulse width high FEC_RXCLK pulse width low Min 5 5 35% 35% Max -- -- 65% 65% Unit ns ns FEC_RXCLK period FEC_RXCLK period
Figure 23 shows MII receive signal timings listed in Table 23.
M3
FEC_RXCLK (input)
M4
FEC_RXD[3:0] (inputs) FEC_RXDV FEC_RXER
M1 M2
Figure 23. MII Receive Signal Timing Diagram
5.15.2
MII Transmit Signal Timing
Table 24 lists MII transmit channel timings. The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. The processor clock frequency must exceed twice the FEC_TXCLK frequency. Table 24. MII Transmit Signal Timing
Num M5 M6 M7 M8 Characteristic FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid FEC_TXCLK pulse width high FEC_TXCLK pulse width low Min 5 -- 35% 35% Max -- 25 65% 65% Unit ns ns FEC_TXCLK period FEC_TXCLK period
Figure 24 shows MII transmit signal timings listed in Table 24.
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 37
Electrical Characteristics
M7
FEC_TXCLK (input)
M5
FEC_TXD[3:0] (outputs) FEC_TXEN FEC_TXER
M6
M8
Figure 24. MII Transmit Signal Timing Diagram
5.15.3
MII Async Inputs Signal Timing
Table 25. MII Async Inputs Signal Timing
Table 25 lists MII asynchronous inputs signal timing.
Num M9
Characteristic FEC_CRS, FEC_COL minimum pulse width
Min 1.5
Max --
Unit FEC_TXCLK period
FEC_CRS FEC_COL M9
Figure 25. MII Async Inputs Timing Diagram
5.15.4
MII Serial Management Channel Timing
Table 26 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. Table 26. MII Serial Management Channel Timing
Num M10 M11 M12 M13 M14 M15 Characteristic FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay) FEC_MDC falling edge to FEC_MDIO output valid (max prop delay) FEC_MDIO (input) to FEC_MDC rising edge setup FEC_MDIO (input) to FEC_MDC rising edge hold FEC_MDC pulse width high FEC_MDC pulse width low Min 0 -- 10 0 Max -- 25 -- -- Unit ns ns ns ns
40% 60% FEC_MDC period 40% 60% FEC_MDC period
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 38 Freescale Semiconductor
Electrical Characteristics
M14
M15
FEC_MDC (output)
M10
FEC_MDIO (output)
M11
FEC_MDIO (input)
M12
M13
Figure 26. MII Serial Management Channel Timing Diagram
5.16
32-Bit Timer Module Timing Specifications
Table 27. Timer Module AC Timing Specifications
Name T1 T2 Characteristic DT0IN / DT1IN / DT2IN / DT3IN cycle time DT0IN / DT1IN / DT2IN / DT3IN pulse width Min 3 1 Max -- -- Unit tCYC tCYC
Table 27 lists timer module AC timings.
5.17
QSPI Electrical Specifications
Table 28. QSPI Modules AC Timing Specifications
Table 28 lists QSPI timings.
Name QS1 QS2 QS3 QS4 QS5 QSPI_CS[3:0] to QSPI_CLK
Characteristic
Min 1 -- 2 9 9
Max 510 10 -- -- --
Unit tCYC ns ns ns ns
QSPI_CLK high to QSPI_DOUT valid. QSPI_CLK high to QSPI_DOUT invalid. (Output hold) QSPI_DIN to QSPI_CLK (Input setup) QSPI_DIN to QSPI_CLK (Input hold)
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 39
Electrical Characteristics
QS1
QSPI_CS[3:0]
QSPI_CLK QS2 QSPI_DOUT QS3 QSPI_DIN QS4 QS5
Figure 27. QSPI Timing
5.18
Num J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14
1
JTAG and Boundary Scan Timing
Table 29. JTAG and Boundary Scan Timing
Characteristics1 TCLK Frequency of Operation TCLK Cycle Period TCLK Clock Pulse Width TCLK Rise and Fall Times Boundary Scan Input Data Setup Time to TCLK Rise Boundary Scan Input Data Hold Time after TCLK Rise TCLK Low to Boundary Scan Output Data Valid TCLK Low to Boundary Scan Output High Z TMS, TDI Input Data Setup Time to TCLK Rise TMS, TDI Input Data Hold Time after TCLK Rise TCLK Low to TDO Data Valid TCLK Low to TDO High Z TRST Assert Time TRST Setup Time (Negation) to TCLK High Symbol fJCYC tJCYC tJCW tJCRF tBSDST tBSDHT tBSDV tBSDZ tTAPBST tTAPBHT tTDODV tTDODZ tTRSTAT tTRSTST Min DC 4 26 0 4 26 0 0 4 10 0 0 100 10 Max 1/4 -- -- 3 -- -- 33 33 -- -- 26 8 -- -- Unit fsys/3 tCYC ns ns ns ns ns ns ns ns ns ns ns ns
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 40 Freescale Semiconductor
Electrical Characteristics
J2 J3 VIH J3
TCLK (input)
J4
VIL J4
Figure 28. Test Clock Input Timing
TCLK
VIL J5
VIH J6
Data Inputs
J7
Input Data Valid
Data Outputs
J8
Output Data Valid
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 29. Boundary Scan (JTAG) Timing
TCLK
VIL J9
VIH J10
TDI TMS
J11
Input Data Valid
TDO
J12
Output Data Valid
TDO
J11
TDO
Output Data Valid
Figure 30. Test Access Port Timing
TCLK
J14
TRST
J13
Figure 31. TRST Timing
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 41
Current Consumption
5.19
Debug AC Timing Specifications
Table 30. Debug AC Timing Specification
Num D0 D1 D2 D3 D41 D5 D6
1
Table 30 lists specifications for the debug AC timing parameters shown in Figure 32.
Characteristic PSTCLK cycle time PSTCLK rising to PSTDDATA valid PSTCLK rising to PSTDDATA invalid DSI-to-DSCLK setup DSCLK-to-DSO hold DSCLK cycle time BKPT assertion time
Min 2 -- 1.5 1 4 5 1
Max 2 3.0 -- -- -- -- --
Units tSYS = 1/fSYS ns ns PSTCLK PSTCLK PSTCLK PSTCLK
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of PSTCLK.
D0
PSTCLK
D1 D2
PSTDDATA[7:0]
Figure 32. Real-Time Trace AC Timing
D5 DSCLK
D3
DSI
Current D4
Next
DSO
Past
Current
Figure 33. BDM Serial Port AC Timing
6
Current Consumption
All current consumption data is lab data measured on a single device using an evaluation board. Table 31 shows the typical power consumption in low-power modes. These current measurements are taken after executing a STOP instruction.
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 42 Freescale Semiconductor
Current Consumption
Table 31. Current Consumption in Low-Power Modes1,2
Mode Stop Mode 3 (Stop 11)5 Voltage 3.3 V 1.5 V Stop Mode 2 (Stop 10)4 3.3 V 1.5 V Stop Mode 1(Stop 01)4 3.3 V 1.5 V Stop Mode 0 (Stop 00)4 3.3 V 1.5 V 3.3 V Wait/Doze 1.5 V 3.3 V Run 1.5 V
1 2 3 4 5
58 MHz (Typ)3 3.9 1.04 4.69 2.69 4.72 15.28 21.65 15.47 22.49 26.79 33.61 56.3
64 MHz (Typ)3 3.92 1.04 4.72 2.69 4.73 16.44 21.68 16.63 22.52 28.85 33.61 60.7
72 MHz (Typ)3 4.0 1.04 4.8 2.70 4.81 17.85 24.33 18.06 25.21 30.81 42.3 65.4
80 MHz (Typ)3 4.0 1.04 4.8 2.70 4.81 19.91 26.13 20.12 27.03 34.47 50.5 73.4
80 MHz (Peak)4 4.0 1.08 4.8 2.75 4.81 20.42
Units
mA 26.16 20.67 39.8 97.4 62.6 132.3
All values are measured with a 3.30V EVDD, 3.30V SDVDD and 1.5V IVDD power supplies. Tests performed at room temperature with pins configured for high drive strength. Refer to the Power Management chapter in the MCF532x Reference Manual for more information on low-power modes. All peripheral clocks except UART0, FlexBus, INTC0, reset controller, PLL, and edge port off before entering low power mode. All code executed from flash. All peripheral clocks on before entering low power mode. All code is executed from flash. See the description of the low-power control register (LCPR) in the MCF532x Reference Manual for more information on stop modes 0-3.
450 Power Consumption (mW) 400 350 300 250 200 150 100 50 0 58 64 72 fsys/3 (MHz)
Figure 34. Current Consumption in Low-Power Modes
Stop 0 - Flash Stop 1 - Flash Stop 2 - Flash Stop 3 - Flash Wait/Doze - Flash Run - Flash
80
80(peak)
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 43
Current Consumption
Table 32. Typical Active Current Consumption Specifications1
fsys/3 Frequency Voltage 3.3V 1.333 MHz 1.5V 3.3V 2.666 MHz 1.5V 3.3V 58 MHz 1.5V 3.3V 64 MHz 1.5V 3.3V 72 MHz 1.5V 3.3V 80 MHz 1.5V
1
Typical2 Active (Flash) 7.73 2.87 8.57 4.37 40.10 65.90 44.40 69.50 53.6 74.6 63.0 79.6
Peak3 7.74 3.56 8.60 5.52 49.3 91.70
Unit
mA 54.0 97.0 63.7 104.7 73.7 112.9
All values are measured with a 3.30 V EVDD, 3.30 V SDVDD and 1.5 V IVDD power supplies. Tests performed at room temperature with pins configured for high drive strength. 2 CPU polling a status register. All peripheral clocks except UART0, FlexBus, INTC0, reset controller, PLL, and edge port disabled. 3 Peak current measured while running a while(1) loop with all modules active.
Figure 35 shows the estimated maximum power consumption.
300 250 200 150 100 50 0 0
Estimated Power Consumption vs. Core Frequency
Power Consumption (mW)
40
80 120 160 Core Frequency (MHz)
200
240
Figure 35. Estimated Maximum Power Consumption
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 44 Freescale Semiconductor
Package Information
7
Package Information
NOTE
The mechanical drawings are the latest revisions at the time of publication of this document. The most up-to-date mechanical drawings can be found at the product summary page located at http://www.freescale.com/coldfire.
This section contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF532x devices.
7.1
Package Dimensions--256 MAPBGA
X Y D
Laser mark for pin A1 identification in this area
Figure 36 shows MCF5328CVM240, MCF53281CVM240, and MCF5329CVM240 package dimensions.
M K A A2 A1 Z 4
256X
5 0.30 Z
E
0.15 Z
Detail K Rotated 90 Clockwise
Notes: 1. 2. 3. 4.
A B C D E F G H J K L M N P R T
Top View
0.20
15 13 11 16 14 12 10 15X
M e
Metalized mark for pin A1 identification in this area
S
7654321
15X
e
S
5.
256X
b 0.25 0.10
3
M M
Dimensions are in millimeters. Interpret dimensions and tolerances per ASME Y14.5M, 1994. Dimension b is measured at the maximum solder ball diameter, parallel to datum plane Z. Datum Z (seating plane) is defined by the spherical crowns of the solder balls. Parallelism measurement shall exclude any effect of mark on top surface of package.
Millimeters Min Max 1.25 1.60 0.27 0.47 1.16 REF 0.40 0.60 17.00 BSC 17.00 BSC 1.00 BSC 0.50 BSC
ZXY Z
Dim
Bottom View
View M-M
A A1 A2 b D E e S
Figure 36. 256 MAPBGA Package Outline
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 45
Package Information
7.2
X Y
Package Dimensions--196 MAPBGA
D Laser mark for pin 1 identification in this area NOTES: 1. Dimensions are in millimeters. 2. Interpret dimensions and tolerances per ASME Y14.5M, 1994. 3. Dimension B is measured at the maximum solder ball diameter, parallel to datum plane Z. 4. Datum Z (seating plane) is defined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package.
Millimeters DIM Min Max
Figure 37 shows the MCF5327CVM240 package dimensions.
M K
E
A A1 A2 b D E e S
1.32 1.75 0.27 0.47 1.18 REF 0.35 0.65 15.00 BSC 15.00 BSC 1.00 BSC 0.50 BSC
Top View
0.20
13X
M
e Metalized mark for pin 1 identification in this area
A B C
S
14 13 12 11 10 9 6 5 4 3 2 1
S
13X
D E F G H J K L M N
5 A A2 0.30 Z
e
A1
Z
4
0.15 Z
Detail K Rotated 90 Clockwise
3
196X
P
b 0.30 Z X Y 0.10 Z
Bottom View
View M-M
Figure 37. 196 MAPBGA Package Dimensions (Case No. 1128A-01)
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 46 Freescale Semiconductor
Revision History
8
Revision History
Table 33. MCF5329DS Document Revision History
Rev. No. 0 0.1 * Initial release. * Added not to Section 7, "Package Information." * Added top view and bottom view where appropriate in mechanical drawings and pinout figures. * Figure 6: Corrected "FB_CLK (75MHz)" label to "FB_CLK (80MHz)" * Corrected MCF5327 196MAPBGA ball map locations in Table 5 for the following signals: RCON, D1, D0, OE, R/W, SD_DQS2, PSTCLK, DDATA[3:0], PST[3:0], EVDD, IVDD, and SD_VDD. Figure 5 was correct. * Updated thermal characteristic values in Table 5. * Updated DC electricals values in Table 7. * Updated Section 3.3, "Supply Voltage Sequencing and Separation Cautions" and subsections. * Updated and added Oscillator/PLL characteristics in Table 8. * Table 9: Swapped min/max for FB1; Removed FB8 & FB9. * Updated SDRAM write timing diagram, Figure 9. * Table 11: Added values for frequency of operation and DD1. * Reworded first paragraph in Section 5.12, "ULPI Timing Specification." * Updated Figure 19. * Replaced figure & table Section 5.13, "SSI Timing Specifications," with slave & master mode versions. * Removed second sentence from Section 5.15.2, "MII Transmit Signal Timing," regarding no minimum frequency requirement for TXCLK. * Removed third and fourth paragraphs from Section 5.15.2, "MII Transmit Signal Timing," as this feature is not supported on this device. * Updated figure & table Section 5.19, "Debug AC Timing Specifications." * Renamed & moved previous version's Section 5.5 "Power Consumption" to Section 6, "Current Consumption." Added additional real-world data to this section as well. * Added MCF53281 device information throughout: features list, family configuration table, ordering information table, signals description table, and relevant package diagram titles * Remove Footnote 1 from Table 11. * Changed document type from Advance Information to Technical Data. Substantive Changes Date of Release 11/2005 3/2006
1
7/2007
2
8/2007
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 47
Revision History
Table 33. MCF5329DS Document Revision History (continued)
Rev. No. 3 Substantive Changes * Corrected MCF53281 in features list table. This device contains CAN, but does not feature the cryptography accelerators. * In pin-multiplexing table, moved MCF53281 label from the MCF5328 column to the MCF5329 column, because this device contains CAN output signals. * Corrected pinouts in Table 5 for 196 MAPBGA device: Changed D[15:1] entry from "F4-F1, G4-G2..." to "F4-F1, G5-G2..." Changed DSO/TDO entry from "P9" to "N9" * Corrected D0 spec in Table 30 from 1.5 x tsys to 2 x tsys for min and max balues. * Updated FlexBus read and write timing diagrams in Figure 7 and Figure 8. * Removed footnote 2 from the IRQ[7:1] alternate functions USBHOST VBUS_EN, USBHOST VBUS_OC, SSI_MCLK, USB_CLKIN, and SSI_CLKIN signals in Table 5. * Updated pinouts for 196 MAPBGA device, MCF5327CVM240 in both Figure 5 and Table 2. The following locations are affected: G10-12, H12-14, J11-14, K12-13, L12-13, M12-14, N13. The following signals are affected: USBOTG_VDD, USBHOST_VSS, USBOTG_M, USBOTG_P, USBHOST_M, USBHOST_P, DRAMSEL, PWM3, PWM1, IRQ[7,4,3,2,1], RESET, TDI/DSI, JTAG_EN, TMS/BKPT. Date of Release 10/2007
4
4/2008
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 48 Freescale Semiconductor
Revision History
THIS PAGE INTENTIONALLY BLANK
MCF532x ColdFire(R) Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 49
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Document Number: MCF5329DS
Rev. 4 04/2008

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